CD4015 CMOS Dual 4-Stage Static Shift Register

The CD4015B consists of two identical, independent, 4-stage serial-input/parallel-output registers
Medium speed operation…12 MHz (typ.) clock rate at VDD – VSS = 10 V, Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Fully static operation, 5-V, 10-V, and 15-V parametric ratings, Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
8 master-slave flip-flops plus input and output buffering, Meets all requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ’B’ Series CMOS Devices”
100% tested for quiescent current at 20 V, Standardized, symmetrical output characteristics, Example Applications: Serial-input/parallel-output data queueing, Serial to parallel data conversion, General-purpose register